The present invention relates to digital storage systems and specifically to digital frame buffers or frame stores used to store digitized images.
Recent advances in electronic still imaging have led to the development of compact solid-state electronic imaging devices having pixel resolutions on the order of megabytes. The "megapixel" imaging devices are of particular interest in the development of hand-held electronic still cameras which would be capable of approaching the image resolution of conventional photographic film technology. While improvements in resolution of electronic imaging devices are welcome, the increase in resolution also presents problems when attempting to employ megapixel imaging devices in compact hand-held electronic still cameras, namely, the need to provide sufficient memory capacity--on the order of several megabytes--to store a plurality of images at data rates on the order of about 13-15 MHz or about 70-75 ns/pixel.
Digital frame buffers capable of handling the required memory capacity and data rates have been developed for use in digital image processors. For example, U.S. Pat. No. 4,725,987 issued to Cates discloses a fast frame store architecture that employs dynamic random access memory (DRAM) devices in a plurality of memory banks. Each memory bank includes a plurality of memory sections having a number of 64K DRAMs equal to the number of bits in the data words to be stored. The 64K DRAMs employed in the frame store disclosed in U.S. Pat. No. 4,725,987 have a basic memory cycle time of about 300 ns which is much slower than the required 70-75 ns/pixel data rate. Thus, double buffering of the input data must be employed to slow the data rate to the memory banks.
The above-described frame store architecture, while being sufficient for use in an image processing system, is not an optimum architecture for an electronic still camera due to the necessity of double buffering the input data. Double buffering requires a large number of system components which is an undesirable feature when attempting to design a compact hand-held camera. Double buffering could be eliminated if the DRAM's employed in the frame buffer were capable of latching and storing data at the higher 70-75 ns/pixel data rate.
Improvements in DRAM technology have led to devices capable of storing four megabytes of information, but the write cycle time of such devices is still on the order of 150 ns. Thus, some type of buffering must still be employed to match the data input rate to the write cycle time of the DRAMs.
Accordingly, it would be desirable to provide an architecture for a compact digital frame store capable of operating at the data rates associated with megapixel imaging devices without requiring the use of double buffering.